View ST7066_3373008.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

st sitronix ST7066 dot matrix lcd controller/driver v1.2 2000/6/13 1 features !" 5 x 8 and 5 x 11 dot matrix possible !" low power operation support: -- 2.7 to 5.5v !" wide range of lcd driver power -- 3.0 to 11v !" correspond to high speed mpu bus interface -- 2 mhz (when v cc = 5v) !" 4-bit or 8-bit mpu interface enabled !" 80 x 8-bit display ram (80 characters max.) !" 9,920-bit character generator rom for a total of 240 character fonts -- 208 character fonts (5 x 8 dot) -- 32 character fonts (5 x 11 dot) !" 64 x 8-bit character generator ram -- 8 character fonts (5 x 8 dot) -- 4 character fonts (5 x 11 dot) !" 16-common x 40-segment liquid crystal display driver !" programmable duty cycles -- 1/8 for one line of 5 x 8 dots with cursor -- 1/11 for one line of 5 x 11 dots & cursor -- 1/16 for two lines of 5 x 8 dots & cursor !" wide range of instruction functions: display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift !" pin function compatibility with hd44780, ks0066 and sed1278 !" automatic reset circuit that initializes the controller/driver after power on !" internal oscillator with external resistors !" low power consumption !" qfp80 and bare chip available description the ST7066 dot-matrix liquid crystal display controller and driver lsi displays alphanumeric, japanese kana characters, and symbols. it can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. since all the functions such as display ram, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. the ST7066 has pin function compatibility with the hd44780, ks0066u and sed1278 that allows the user to easily replace it with an ST7066. the ST7066 character generator rom is extended to generate 208 5 x 8 dot character fonts and 32 5 x 11 dot character fonts for a total of 240 different character fonts. the low power supply (2.7v to 5.5v) of the ST7066 is suitable for any portable battery-driven product requiring low power dissipation. the ST7066 lcd driver consists of 16 common signal drivers and 40 segment signal drivers which can extend display size by cascading segment driver st7065 or st7063. the maximum display size can be either 80 characters in 1-line display or 40 characters in 2-line display. a single ST7066 can display up to one 8-character line or two 8-character lines. product name support character ST7066-0a english / japan ST7066-0b english / european
ST7066 v1.2 2000/6/13 2 block diagram timing generator 16-bit shift registe r common signal driver display data ram (ddram) 80x8 bits 40-bit latch circuit segment signal driver 40-bit shift registe r lcd drive voltage selector cpg instruction register (ir) instruction decoder reset circuit mpu interface input/ output buffer address counter character generator rom (cgrom) 9,920 bits character generator ram (cgram) 64 bits cursor and blink controller data register (dr) busy flag parallel/serial converter and attribute circuit gnd vcc v1 v2 v3 v4 v5 osc1 osc2 cl1 cl2 m d com1 to com16 seg1 to seg40 rs rw e db4 to db7 db0 to db3
ST7066 v1.2 2000/6/13 3 pad arrangement ST7066 chip size : 2300x3000 coordinate : pad center origin : chip center pad size : 90x90 unit : um 80 1 64 24 41 "ST7066" marking : easy to find the pad (0,0) subtrate:v dd
ST7066 v1.2 2000/6/13 4 pad location coordinates pad no. pad no. pad no. pad no. function function function function x x x x y y y y 1 seg22 -1040 1400 2 seg21 -1040 1270 3 seg20 -1040 1140 4 seg19 -1040 1020 5 seg18 -1040 900 6 seg17 -1040 780 7 seg16 -1040 660 8 seg15 -1040 540 9 seg14 -1040 420 10 seg13 -1040 300 11 seg12 -1040 180 12 seg11 -1040 60 13 seg10 -1040 -60 14 seg9 -1040 -180 15 seg8 -1040 -300 16 seg7 -1040 -420 17 seg6 -1040 -540 18 seg5 -1040 -660 19 seg4 -1040 -780 20 seg3 -1040 -900 21 seg2 -1040 -1020 22 seg1 -1040 -1140 23 gnd -1040 -1270 24 osc1 -1040 -1400 25 osc2 -910 -1400 26 v1 -780 -1400 27 v2 -660 -1400 28 v3 -540 -1400 29 v4 -420 -1400 30 v5 -300 -1400 31 cl1 -180 -1400 32 cl2 -60 -1400 33 vcc 60 -1400 34 m 180 -1400 35 d 300 -1400 36 rs 420 -1400 37 rw 540 -1400 38 e 660 -1400 39 db0 780 -1400 40 db1 910 -1400 pad no. pad no. pad no. pad no. function function function function x x x x y y y y 41 db2 1040 -1400 42 db3 1040 -1270 43 db4 1040 -1140 44 db5 1040 -1020 45 db6 1040 -900 46 db7 1040 -780 47 com1 1040 -660 48 com2 1040 -540 49 com3 1040 -420 50 com4 1040 -300 51 com5 1040 -180 52 com6 1040 -60 53 com7 1040 60 54 com8 1040 180 55 com9 1040 300 56 com10 1040 420 57 com11 1040 540 58 com12 1040 660 59 com13 1040 780 60 com14 1040 900 61 com15 1040 1020 62 com16 1040 1140 63 seg40 1040 1270 64 seg39 1040 1400 65 seg38 910 1400 66 seg37 780 1400 67 seg36 660 1400 68 seg35 540 1400 69 seg34 420 1400 70 seg33 300 1400 71 seg32 180 1400 72 seg31 60 1400 73 seg30 -60 1400 74 seg29 -180 1400 75 seg28 -300 1400 76 seg27 -420 1400 77 seg26 -540 1400 78 seg25 -660 1400 79 seg24 -780 1400 80 seg23 -910 1400
ST7066 v1.2 2000/6/13 5 pin functions name number i/o interfaced with function rs 1 i mpu select registers. 0: instruction register (for write) busy flag: address counter (for read) 1: data register (for write and read) r/w 1 i mpu select read or write. 0: write 1: read e 1 i mpu starts data read/write. db4 to db7 4 i/o mpu four high order bi-directional tristate data bus pins. used for data transfer and receive between the mpu and the ST7066. db7 can be used as a busy flag. db0 to db3 4 i/o mpu four low order bi-directional tristate data bus pins. used for data transfer and receive between the mpu and the ST7066. these pins are not used during 4-bit operation. cl1 1 o extension driver clock to latch serial data d sent to the extension driver cl2 1 o extension driver clock to shift serial data d m 1 o extension driver switch signal for converting the liquid crystal drive waveform to ac d 1 o extension driver character pattern data corresponding to each segment signal com1 to com16 16 o lcd common signals that are not used are changed to non-selection waveform. com9 to com16 are non-selection waveforms at 1/8 duty factor and com12 to com16 are non-selection waveforms at 1/11 duty factor. seg1 to seg40 40 o lcd segment signals v1 to v5 5 - power supply power supply for lcd drive v cc - v5 = 11 v (max) v cc , gnd 2 - power supply v cc : 2.7v to 5.5v, gnd: 0v osc1, osc2 2 oscillation resistor clock when crystal oscillation is performed, a resistor must be connected externally. when the pin input is an external clock, it must be input to osc1. note: 1. vcc>=v1>=v2>=v3>=v4>=v5 must be maintained 2. two clock options: r osc1 1 osc2 1 osc1 1 osc2 1 clock input r=91k (vcc=5v) r=75k
ST7066 v1.2 2000/6/13 6 function description system interface this chip has all two kinds of interface type with mpu : 4-bit bus and 8-bit bus. 4-bit bus or 8-bit bus is selected by dl bit in the instruction register. during read or write operation, two 8-bit registers are used. one is data register (dr), the other is instruction register(ir). the data register(dr) is used as temporary data storage place for being written into or read from ddram/cgram, target ram is selected by ram address setting instruction. each internal operation, reading from or writing into ram, is done automatically. so to speak, after mpu reads dr data, the data in the next ddram/cgram address is transferred into dr automatically. also after mpu writes data to dr, the data in dr is transferred into ddram/cgram automatically. the instruction register(ir) is used only to store instruction code transferred from mpu. mpu cannot use it to read instruction data. to select register, use rs input pin in 4-bit/8-bit bus mode. table 1. various kinds of operations according to rs and r/w bits. rs rw operation l l instruction write operation (mpu writes instruction code into ir) l h read busy flag(db7) and address counter (db0 ~ db6) h l data write operation (mpu writes data into dr) h h data read operation (mpu reads data from dr) busy flag (bf) when bf = "high?, it indicates that the internal operation is being processed. so during this time the next instruction cannot be accepted. bf can be read, when rs = low and r/w = high (read instruction operation), through db7 port. before executing the next instruction, be sure that bf is not high. address counter (ac) address counter(ac) stores ddram/cgram address, transferred from ir. after writing into (reading from) ddram/cgram, ac is automatically increased (decreased) by 1. when rs = "low" and r/w = "high", ac can be read through db0 ~ db6 ports.
ST7066 v1.2 2000/6/13 7 display data ram (ddram) display data ram (ddram) stores display data represented in 8-bit character codes. its extended capacity is 80 x 8 bits, or 80 characters. the area in display data ram (ddram) that is not used for display can be used as general data ram. see figure 1 for the relationships between ddram addresses and positions on the liquid crystal display. the ddram address (a dd ) is set in the address counter (ac) as hexadecimal. !" 1-line display (n = 0) (figure 2) when there are fewer than 80 display characters, the display begins at the head position. for example, if using only the ST7066, 8 characters are displayed. see figure 3. when the display shift operation is performed, the ddram address shifts. see figure 3. figure 1 ddram address figure 1 ddram address figure 1 ddram address figure 1 ddram address figure 2 1 figure 2 1 figure 2 1 figure 2 1- - - -line display line display line display line display figure 3 1 figure 3 1 figure 3 1 figure 3 1- - - -line by 8 line by 8 line by 8 line by 8- - - -character display example character display example character display example character display example !" 2-line display (n = 1) (figure 4) case 1: when the number of display characters is less than 40 2 lines, the two lines are displayed from the head. note that the first line end address and th e second line start address are not consecutive. for example, when just the ST7066 is used, 8 characters 2 lines are displayed. see figure 5. ac6 ac5 ac4 ac3 ac2 ac1 ac0 1 0 0 1 1 1 1 high order bits low order bits ac example: ddram address 4f 00 01 02 03 04 05 4d 4e 4f ddram address ??????.. 1 2 3 4 5 6 80 79 78 display position (digit) 00 01 02 03 04 05 06 07 ddram address 1 2 3 4 5 6 8 7 display position 08 01 02 03 04 05 06 07 00 01 02 03 04 05 06 4f for shift left for shift right
ST7066 v1.2 2000/6/13 8 when display shift operation is performed, the ddram address shifts. see figure 5. figure 4 2 figure 4 2 figure 4 2 figure 4 2- - - -line display line display line display line display figure 5 2 figure 5 2 figure 5 2 figure 5 2- - - -line by 8 line by 8 line by 8 line by 8- - - -character display example character display example character display example character display example case 2: for a 16-character 2-line display, the ST7066 can be extended using one 40-output extension driver. see figure 6. when display shift operation is performed, the ddram address shifts. see figure 6. figure 6 2 figure 6 2 figure 6 2 figure 6 2- - - -line by 16 line by 16 line by 16 line by 16- - - -character display example character display example character display example character display example ddram address display position 00 01 02 03 04 05 06 27 for shift right 00 01 02 03 04 05 06 07 1 2 3 4 5 6 8 7 40 41 42 43 44 45 46 47 08 01 02 03 04 05 06 07 for shift left 48 41 42 43 44 45 46 47 40 41 42 43 44 45 46 67 ddram address display position for shift right 00 01 02 03 04 05 06 07 1 2 3 4 5 6 8 7 40 41 42 43 44 45 46 47 for shift left 08 01 02 03 04 05 06 07 48 41 42 43 44 45 46 47 00 01 02 03 04 05 06 27 40 41 42 43 44 45 46 67 08 09 0a 0b 0c 0d 0e 0f 9 10 11 12 13 14 16 15 48 49 4a 4b 4c 4d 4e 4f 10 09 0a 0b 0c 0d 0e 0f 50 49 4a 4b 4c 4d 4e 4f 08 09 0a 0b 0c 0d 0e 07 48 49 4a 4b 4c 4d 4e 47 ddram address (hexadecimal) 00 01 02 03 04 05 25 26 27 ??????.. 1 2 3 4 5 6 40 39 38 display position 40 41 42 43 44 45 65 66 67 ??????..
ST7066 v1.2 2000/6/13 9 character generator rom (cgrom) the character generator rom generates 5 x 8 dot or 5 x 11 dot character patterns from 8-bit character codes. it can generate 208 5 x 8 dot character patterns and 32 5 x 11 dot character patterns. user-defined character patterns are also available by mask-programmed rom. character generator ram (cgram) in the character generator ram, the user can rewrite character patterns by program. for 5 x 8 dots, eight character patterns can be written, and for 5 x 11 dots, four character patterns can be written. write into ddram the character codes at the addresses shown as the left column of table 4 to show the character patterns stored in cgram. see table 5 for the relationship between cgram addresses and data and display patterns. areas that are not used for display can be used as general data ram. timing generation circuit the timing generation circuit generates timing signals for the operation of internal circuits such as ddram, cgrom and cgram. ram read timing for display and internal operation timing by mpu access are generated separately to avoid interfering with each other. therefore, when writing data to ddram, for example, there will be no undesirable interference, such as flickering, in areas other than the display area. lcd driver circuit lcd driver circuit has 16 common and 40 segment signals for lcd driving. data from cgram/cgrom is transferred to 40 bit segment latch serially, and then it is stored to 40 bit shift latch. when each common is selected by 16 bit common register, segment data also output through segment driver from 40 bit segment latch. in case of 1-line display mode, com1 ~ com8 have 1/8 duty or com1 ~ com11 have 1/11duty , and in 2-line mode, com1 ~ com16 have 1/16 duty ratio. cursor/blink control circuit it can generate the cursor or blink in the cursor/blink control circuit. the cursor or the blink appears in the digit at the display data ram address set in the address counter.
ST7066 v1.2 2000/6/13 10 table 4 correspondence between character codes and character patterns (rom code: 0a)
ST7066 v1.2 2000/6/13 11 table 4(cont.) (rom code: 0b)
ST7066 v1.2 2000/6/13 12 character code (ddram data) cgram address character patterns (cgram data) b7 b6 b5 b4 b3 b3 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 - 0 0 0 0 0 0 1 1 1 - - - 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 0 1 0 1 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 - 0 0 1 0 0 0 1 1 1 - - - 0 0 0 0 0 table 5 relationship between cgram addresses, character codes (ddram) and character patterns (cgram data) notes: 1. character code bits 0 to 2 correspond to cgram address bits 3 to 5 (3 bits: 8 types). 2. cgram address bits 0 to 2 designate the character pattern line position. the 8th line is the cursor position and its display is formed by a logical or with the cursor. maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. if the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence. 3. character pattern row positions correspond to cgram data bits 0 to 4 (bit 4 being at the left). 4. as shown table 5, cgram character patterns are selected when character code bits 4 to 7 are all 0. however, since character code bit 3 has no effect, the r display example above can be selected by either character code 00h or 08h. 5. 1 for cgram data corresponds to display selection and 0 to non-selection. ?-?: indicates no effect.
ST7066 v1.2 2000/6/13 13 instructions there are four categories of instructions that: !" designate ST7066 functions, such as display format, data length, etc. !" set internal ram addresses !" perform data transfer with internal ram !" others instruction table: instruction code instruction rs rw db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 description description time (270khz) clear display 0 0 0 0 0 0 0 0 0 1 write "20h" to ddram. and set ddram address to "00h" from ac 1.52 ms return home 0 0 0 0 0 0 0 0 1 x set ddram address to "00h" from ac and return cursor to its original position if shifted. the contents of ddram are not changed. 1.52 ms entry mode set 0 0 0 0 0 0 0 1 i/d s sets cursor move direction and specifies display shift. these operations are performed during data write and read. 37 us display on/off 0 0 0 0 0 0 1 d c b d=1: entire display on c=1: cursor on b=1: cursor position on 37 us cursor or display shift 0 0 0 0 0 1 s/c r/l x x set cursor moving and display shift control bit, and the direction, without changing ddram data. 37 us function set 0 0 0 0 1 dl n f x x dl: interface data is 8/4 bits nl: number of line is 2/1 f: font size is 5x11/5x8 37 us set cgram address 0 0 0 1 ac 5 ac 4 ac 3 ac 2 ac 1 ac 0 set cgram address in address counter 37 us set ddram address 0 0 1 ac 6 ac 5 ac 4 ac 3 ac 2 ac 1 ac 0 set ddram address in address counter 37 us read busy flag and address 0 1 bf ac 6 ac 5 ac 4 ac 3 ac 2 ac 1 ac 0 whether during internal operation or not can be known by reading bf. the contents of address counter can also be read. 0 us write data to ram 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data into internal ram (ddram/cgram) 43 us read data from ram 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read data from internal ram (ddram/cgram) 43 us note: be sure the ST7066 is not in the busy state (bf = 0) before sending an instruction from the mpu to the ST7066. if an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. refer to instruction table for the list of each instruction execution time.
ST7066 v1.2 2000/6/13 14 instruction description ! ! ! !" " " " clear display clear all the display data by writing "20h" (space code) to all ddram address, and set ddram address to "00h" into ac (address counter). return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. make entry mode increment (i/d = "1"). ! ! ! !" " " " return home return home is cursor return home instruction. set ddram address to "00h" into the address counter. return cursor to its original site and return display to its original status, if shifted. contents of ddram does not change. ! ! ! !" " " " entry mode set set the moving direction of cursor and display. i/d : increment / decrement of ddram address (cursor or blink) when i/d = "high", cursor/blink moves to right and ddram address is increased by 1. when i/d = "low", cursor/blink moves to left and ddram address is decreased by 1. * cgram operates the same as ddram, when read from or write to cgram. s: shift of entire display when ddram read (cgram read/write) operation or s = "low", shift of entire display is not performed. if s = "high" and ddram write operation, shift of entire display is performed according to i/d value (i/d = "1" : shift left, i/d = "0" : shift right). s i/d description h h shift the display to the left h l shift the display to the right 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 code code code rs rs rs rw rw rw db7 db7 db7 db6 db6 db6 db5 db5 db5 db4 db4 db4 db1 db1 db1 db2 db2 db2 db3 db3 db3 0 1 i/d 1 x s db0 db0 db0
ST7066 v1.2 2000/6/13 15 ! ! ! !" " " " display on/off control display/cursor/blink on/off 1 bit register. d : display on/off control bit when d = "high", entire display is turned on. when d = "low", display is turned off, but display data is remained in ddram. c : cursor on/off control bit when c = "high", cursor is turned on. when c = "low", cursor is disappeared in current display, but i/d register remains its data. b : cursor blink on/off control bit when b = "high", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. when b = "low", blink is off. ! ! ! !" " " " cursor or display shift without writing or reading of display data, shift right/left cursor position or display. this instruction is used to correct or search display data. during 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. note that display shift is performed simultaneously in all the line. when displayed data is shifted repeatedly, each line shifted individually. when display shift is performed, the contents of address counter are not changed. s/c r/l description ac value l l shift cursor to the left ac=ac-1 l h shift cursor to the right ac=ac+1 h l shift display to the left. cursor follows the display shift ac=ac h h shift display to the right. cursor follows the display shift ac=ac ! ! ! !" " " " function set control display/cursor/blink on/off 1 bit register. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 dl 1 s/c n d r/l f code code code rs rs rs rw rw rw db7 db7 db7 db6 db6 db6 db5 db5 db5 db4 db4 db4 db1 db1 db1 db2 db2 db2 db3 db3 db3 c x x b x x db0 db0 db0
ST7066 v1.2 2000/6/13 16 dl : interface data length control bit when dl = "high", it means 8-bit bus mode with mpu. when dl = "low", it means 4-bit bus mode with mpu. so to speak, dl is a signal to select 8-bit or 4-bit bus mode. when 4-bit bus mode, it needs to transfer 4-bit data by two times. n : display line number control bit when n = "low", it means 1-line display mode. when n = "high", 2-line display mode is set. f : display font type control bit when f = "low", it means 5 x 8 dots format display mode when f = "high", 5 x11 dots format display mode. n f no. of display lines character font duty factor l l 1 5x8 1/8 l h 1 5x11 1/11 h x 2 5x8 1/16 ! ! ! !" " " " set cgram address set cgram address to ac. this instruction makes cgram data available from mpu. ! ! ! !" " " " set ddram address set ddram address to ac. this instruction makes ddram data available from mpu. when 1-line display mode (n = 0), ddram address is from "00h" to "4fh". in 2-line display mode (n = 1), ddram address in the 1st line is from "00h" to "27h", and ddram address in the 2nd line is from "40h" to "67h". 0 0 1 ac6 ac5 ac4 ac3 ac2 code rs rw db7 db6 db5 db4 db1 db2 db3 ac1 ac0 db0 0 0 0 1 ac5 ac4 ac3 ac2 code rs rw db7 db6 db5 db4 db1 db2 db3 ac1 ac0 db0
ST7066 v1.2 2000/6/13 17 ! ! ! !" " " " read busy flag and address when bf = ?high?, indicates that the internal operation is being processed.so during this time the next instruction cannot be accepted. the address counter (ac) stores ddram/cgram addresses, transferred from ir. after writing into (reading from) ddram/cgram, ac is automatically increased (decreased) by 1. ! ! ! !" " " " write data to cgram or ddram write binary 8-bit data to ddram/cgram. the selection of ram from ddram, cgram, is set by the previous address set instruction : ddram address set, cgram address set. ram set instruction can also determine the ac direction to ram. after write operation, the address is automatically increased/decreased by 1, according to the entry mode. ! ! ! !" " " " read data from cgram or ddram read binary 8-bit data from ddram/cgram. the selection of ram is set by the previous address set instruction. if address set instruction of ram is not performed before this instruction, the data that read first is invalid, because the direction of ac is not determined. if you read ram data several times without ram address set instruction before read operation, you can get correct ram data from the second, but the first data would be incorrect, because there is no time margin to transfer ram data. in case of ddram read operation, cursor shift instruction plays the same role as ddram address set instruction : it also transfer ram data to output data register. after read operation address counter is automatically increased/decreased by 1 according to the entry mode. after cgram read operation, display shift may not be executed correctly. * in case of ram write operation, after this ac is increased/decreased by 1 like read operation. in this time, ac indicates the next address position, but you can read only the previous data by read instruction. 1 1 0 1 d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 code code rs rs rw rw db7 db7 db6 db6 db5 db5 db4 db4 db1 db1 db2 db2 db3 db3 d1 d1 d0 d0 db0 db0 0 1 bf ac6 ac5 ac4 ac3 ac2 code rs rw db7 db6 db5 db4 db1 db2 db3 ac1 ac0 db0
ST7066 v1.2 2000/6/13 18 reset function initializing by internal reset circuit an internal reset circuit automatically initializes the ST7066 when the power is turned on. the following instructions are executed during the initialization. the busy flag (bf) is kept in the busy state until the initialization ends (bf = 1). the busy state lasts for 10 ms after vcc rises to 4.5 v. 1. display clear 2. function set: dl = 1; 8-bit interface data n = 0; 1-line display f = 0; 5 8 dot character font 3. display on/off control: d = 0; display off c = 0; cursor off b = 0; blinking off 4. entry mode set: i/d = 1; increment by 1 s = 0; no shift note: if the electrical characteristics conditions listed under the table power supply conditions using internal reset circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the ST7066. for such a case, initialization must be performed by the mpu as explain by the following figure .
ST7066 v1.2 2000/6/13 19 8-bit interface: power on wait time > 15ms after vcc > 4.5v 0 0 0 0 1 1 x x x x wait time > 4.1ms 0 0 0 0 1 1 x x x x wait time > 100us 0 0 0 0 1 1 x x x x 0 0 0 0 1 1 n f x x 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 i/d s initialization end bf cannot be checked before the instruction function set bf cannot be checked before the instruction function set bf cannot be checked before the instruction function set bf can be checked after the following instructions function set display off display clear entry mode set rs rw d7 d6 d5 d4 d3 d2 d1 d0
ST7066 v1.2 2000/6/13 20 4-bit interface: power on wait time > 15ms after vcc > 4.5v 0 0 0 0 1 1 wait time > 4.1ms 0 0 0 0 1 1 wait time > 100us 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 n f initialization end bf cannot be checked before the instruction function set bf cannot be checked before the instruction function set bf cannot be checked before the instruction function set bf can be checked after the following instructions function set display off display clear entry mode set rs rw d7 d6 d5 d4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 i/d s
ST7066 v1.2 2000/6/13 21 interfacing to the mpu the ST7066 can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit mpu. !" for 4-bit interface data, only four bus lines (db4 to db7) are used for transfer. bus lines db0 to db3 are disabled. the data transfer between the ST7066 and the mpu is completed after the 4-bit data has been transferred twice. as for the order of data transfer, the four high order bits (for 8-bit operation, db4 to db7) are transferred before the four low order bits (for 8-bit operation, db0 to db3). the busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. two more 4-bit operations then transfer the busy flag and address counter data. !" for 8-bit interface data, all eight bus lines (db0 to db7) are used. supply voltage for lcd drive there are different voltages that supply to ST7066?s pin (v1 - v5) to obtain lcd drive waveform. the relations of the bias, duty factor and supply voltages are shown as below: duty factor 1/8, 1/11 1/16 bias supply voltage 1/4 1/5 v1 vcc - 1/4v lcd vcc - 1/5v lcd v2 vcc - 1/2v lcd vcc - 2/5v lcd v3 vcc - 1/2v lcd vcc - 3/5v lcd v4 vcc - 3/4v lcd vcc - 4/5v lcd v5 vcc - v lcd vcc- v lcd r r r r r vr r r r r vr v1 v1 vcc v2 v3 v4 v5 vcc v2 v3 v4 v5 -5v +5v -5v 1/4 bias (1/8, 1/11 duty cycle) 1/5 bias (1/16 duty cycle) v lcd v lcd
ST7066 v1.2 2000/6/13 22 timing characteristics !" writing data from mpu to ST7066 !" reading data from ST7066 to mpu rs r/w e db0-db7 v ih1 v il1 v ih1 v il1 t as t ah t pw t c valid data t r t ah t h t dsw rs r/w e db0-db7 v ih1 v il1 v ih1 v il1 t as t ah t ah t pw t c t c valid data valid data t r t ah t h t h t ddr
ST7066 v1.2 2000/6/13 23 absolute maximum ratings characteristics symbol value power supply voltage v cc -0.3v to +7.0v lcd driver voltage v lcd -0.3v to +13.0v input voltage v in -0.3v to v cc +0.3v operating temperature t a -20 o c to +70 o c storage temperature t sto -55 o c to +125 o c dc characteristics (t a = 25 o c, v cc = 2.7v - 5.5v) symbol characteristics test condition min. typ. max. unit v cc operating voltage - 2.7 - 5.5 v v lcd lcd voltage v cc -v5 3.0 - 11 v i cc power supply current f osc = 270khz, v cc =5v - 0.3 0.6 ma v ih1 input high voltage (except osc1) - 2.2 - v cc v v il1 input low voltage (except osc1) - -0.3 - 0.6 v v ih2 input high voltage (osc1) - v cc -1 - v cc v v il2 input low voltage (osc2) - - - 1.0 v v oh1 output high voltage (db0 - db7) i oh = -0.1ma 2.4 - v cc v v ol1 output low voltage (db0 - db7) i ol = 0.1ma - - 0.4 v v oh2 output high voltage (except db0 - db7) i oh = -0.04ma 0.9v cc - v cc v v ol2 output low voltage (except db0 - db7) i ol = 0.04ma - - 0.1v cc v r com common resistance v lcd = 4v, i d = 0.05ma - 2 20 k ? r seg segment resistance v lcd = 4v, i d = 0.05ma - 2 30 k ? i leak input leakage current v in = 0v to v cc -1 - 1 a i pup pull up mos current v cc = 5v 10 50 120 a
ST7066 v1.2 2000/6/13 24 ac characteristics (t a = 25 o c, v cc = 5v) symbol characteristics test condition min. typ. max. unit internal clock operation f osc osc frequency r = 91k ? 190 270 350 khz external clock operation f ex external frequency - 125 250 350 khz duty cycle - 45 50 55 % t r ,t f rise/fall time - - - 0.2 s write mode (writing data from mpu to ST7066) t c enable cycle time pin e 400 - - ns t pw enable pulse width pin e 150 - - ns t r ,t f enable rise/fall time pin e - - 25 ns t as address setup time pins: rs,rw,e 30 - - ns t ah address hold time pins: rs,rw,e 10 - - ns t dsw data setup time pins: db0 - db7 40 - - ns t h data hold time pins: db0 - db7 10 - - ns read mode (reading data from ST7066 to mpu) t c enable cycle time pin e 400 - - ns t pw enable pulse width pin e 150 - - ns t r ,t f enable rise/fall time pin e - - 25 ns t as address setup time pins: rs,rw,e 30 - - ns t ah address hold time pins: rs,rw,e 10 - - ns t ddr data setup time pins: db0 - db7 - - 100 ns t h data hold time pins: db0 - db7 10 - - ns interface mode with lcd driver(st7065) t cwh clock pulse with high pins: cl1, cl2 800 - - ns t cwl clock pulse with low pins: cl1, cl2 800 - - ns t cst clock setup time pins: cl1, cl2 500 - - ns t su data setup time pin: d 300 - - ns t dh data hold time pin: d 300 - - ns t dm m delay time pin: m -1000 - 1000 ns
ST7066 v1.2 2000/6/13 25 the relations between oscillation frequency and lcd frame frequency assume the oscillation frequency is 270khz, 1 clock cycle time = 3.7us 1. 1/8 duty 2. 1/11 duty 3. 1/16 duty 400 clocks 1 2 3 4 ------ 1 8 2 v5 v4 v2(v3) v1 vcc com1 1 frame = 3.7(us) x 400 x 8 = 11850(us) = 11.9(ms) 1 frame 400 clocks 1 2 3 4 ------ 1 11 2 v5 v4 v2(v3) v1 vcc com1 1 frame = 3.7(us) x 400 x 11 = 16300(us) = 16.3(ms) 1 frame 200 clocks 1 2 3 4 ------ 1 16 2 v5 v4 v2 v1 vcc com1 1 frame = 3.7(us) x 200 x 16 = 11850(us) = 11.9(ms) 1 frame v3
ST7066 v1.2 2000/6/13 26 i/o pad configuration input pad: e (no pull-up) input pad: rs, rw(with pull-up) output pad: cl1, cl2, m, d i/o pad: db0 ? db7 data enable
ST7066 v1.2 2000/6/13 27 lcd and ST7066 connection 1. 5x8 dots, 8 characters x 1 line (1/4 bias, 1/8 duty) com1 . . . . . com8 ST7066 seg1 . . . seg40 lcd panel: 8 characters x 1 line 2. 5x11 dots, 8 characters x 1 line (1/4 bias, 1/11 duty) com1 . . . . . . . . com11 ST7066 seg1 . . . . . . . seg40 lcd panel: 8 characters x 1 line
ST7066 v1.2 2000/6/13 28 3. 5x8 dots, 8 characters x 2 line (1/5 bias, 1/16 duty) com1 . . . . . com8 ST7066 seg1 . . . . . . . seg40 lcd panel: 8 characters x 2 line com9 . . . . . com16 4. 5x8 dots, 16 characters x 1 line (1/5 bias, 1/16 duty) com1 . . . . . com8 ST7066 seg1 . . . . seg40 lcd panel: 16 characters x 1 line com9 . . . . . com16
ST7066 v1.2 2000/6/13 29 ST7066 application circuit dot matrix lcd panel ST7066 com1-16 seg1-40 d vcc gnd cl2 cl1 m v1 v2 v3 v4 v5 y1-y40 dl1 vdd fcs shl1 shl2 gnd st7065 vee v1 v6 v3 v4 v5 v2 dr2 dl2 dr1 cl1 cl2 m y1-y40 dl1 vdd fcs shl1 shl2 gnd st7065 vee v1 v6 v3 v4 v5 v2 dr2 dl2 dr1 cl1 cl2 m db0-db7 to mpu reg. reg. reg. reg. reg. reg. vcc(+5v ) -v or gnd note: r= 2.2k ~ 10k, vr= 10k~30k

▲Up To Search▲

Price & Availability of ST7066

	To Download ST7066 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .